AMD starts Venice EPYC production ramp on TSMC 2nm in Taiwan

AMD said its 6th Gen EPYC Venice server CPU has entered production ramp in Taiwan on TSMC's 2nm process, with a later ramp planned at TSMC's Arizona fab. AMD calls Venice the first high-performance computing product to enter production on 2nm, and says the follow-on Verano, which adds LPDDR memory support, will also use the node. The release gave no shipment, unit or performance figures, so the revenue effect is not yet quantified.

• Venice ramping in Taiwan on TSMC 2nm
• Arizona ramp is a later plan, not a current production fact
• Verano to follow on TSMC 2nm with LPDDR memory support
• No unit, pricing or performance figures disclosed